Currently all of these optimizations are just what the spec recommends. I don't know what hardware implements what.
lui ra, imm[31:12]; jalr ra, imm[11:0](ra) 1 |
auipc ra, imm[31:12]; jalr ra, imm[11:0](ra) 1 |
mulh rdh, rs1, rs2; mul rdl, rs1, rs2 1 |
mulhu rdh, rs1, rs2; mul rdl, rs1, rs2 1 |
mulhsu rdh, rs1, rs2; mul rdl, rs1, rs2 1 |
div rdq, rs1, rs2; rem rdr, rs1, rs2 (rdq != rs1, rdq != rs2) 1 |
divu rdq, rs1, rs2; remu rdr, rs1, rs2 (rdq != rs1, rdq != rs2) 1 |
"Link register" means ra or t0.
| Instruction | Behaviour on RAS |
|---|---|
jal rd, imm | Push if rd is link register. 1 |
jalr rd, imm(rs1) | Pop if rs1 is link register and not the same as rd. Then push if rd is link register. 1 |